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NTE1639 Integrated Circuit
CMOS Clock Generator/Driver for BBDs
Description: The NTE1639 is a CMOS LSI Clock Generator ina 8-Lead DIP type package capable of generating two phase clock signals of low output impedance for use as a BBD driver. The built-in VGG power supply circuit provides the proper voltages needed for driving BBDs such as the NTE1641. Features: D BBD Direct Driving Capability of up to two BBD's D Self and Separate Oscillations. D Two Phase Clock Output (Duty: 1/2) D Built-in VGG Voltage Generator for Driving the NTE1641 BBD. D Single Power Supply: -8V to -16V. Applications: D BBD Clock Generator/Driver. Absolute Maximum Ratings: (TA = +25C unless otherwise specified) Drain Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18V to +0.3V Input/Output Pin Voltage, VI, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD -0.3V to +0.3V Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mW Operating Ambient Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10 to +70C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30 to +125C Recommended Operating Conditions: (TA = +25C unless otherwise specified) Item Drain Supply Voltage Symbol VDD Condition GND = 0V Min -8 Typ -15 Max -16 Unit V
Electrical Characteristics: (TA = +25C, VDD = -15V, GND = 0V unless otherwise specified) Parameter Input Drain Current Total Power Dissipation OX1 Input Pin Voltage "H" Level Voltage "L" Level Input Leakage Current OX2 Output Pin Output Current "H" Level Output Current "L" Level Output Leakage Current OX3 Output pin Output Current "H" Level Output Current "L" Level Output Leakage Current CP1, CP2 output pin Output Current "H" Level Output Current "L" Level Output Leakage Current IOH(3) IOL(3) ILOL(3) VO = -1V VO = -14V VO = VDD VO = GND 10 10 - - - - - - - - 30 30 mA mA A A V IOH(2) IOL(2) ILOL(2) VO = -1V VO = -14V VO = VDD VO = GND 1.5 2 - - - - - - - - 30 30 mA mA A A IOH(1) IOL(1) ILOL(1) VO = -1V VO = -14V VO = VDD VO = GND 0.6 0.5 - - - - - - - - 30 30 mA mA A A VIH VIL ILeak VI = 0V to -15V 0 VDD+1 - - - - -1 VDD 30 V V A Symbol IDD Ptot Test Condition No load Clock Output 40kHZ Min - - Typ 3 45 Max - - Unit mA mW
VGG OUT output pin (Note 1) Output Voltage VGG(Out) -14
Note 1. This pin generates the VGG voltage for a BBD manufactured by NTE. So therefore, it might not be applicable for other devices. In any case, the VGG(OUT) changes by the following formula depending on the value of VDD.
VGG(OUT)
14 VDD 15
Pin Descriptions: Pin No. Symbol 1 2 GND CP1 Pin Name Ground Clock Output 1 Description Connected to GND of the circuit. This pin outputs a clock signal that is the reverse phase of CP2 with a Duty Cycle of 1/2 the frequency of oscillation. -15V is applied This pin outputs a clock signal that is a the reverse phase of CP1 R, C are connected for the In case of separate excitainternal clock. tion, OX3 and OX2 are opened and OX1 is set to OSC input. -14V is output. (VDD = -15V) VGG OUT = 14/15VDD.
3 4 5 6 7 8
VDD CP2 OX3 OX2 OX1 VGG OUT
VDD apply Clock Output 2 OSC connections to C1, R2, and R1 separately VGG Voltage Output
The Maximum Clock Frequency: The upper limit value of the clock frequency is determined by the load capacitance and power consumption. The maximum power dissipation for the NTE1639 is PD = 200mW. If the clock frequency of the load capacitance is increased, the power consumption will be increased. Accordingly, in order to utilize this device with a dissipation less than the permissible value, it is necessary to select adequate values for the clock frequency and load capacitance. By connecting a resistance to the clock output pin, it is possible to increase the value of the maximum clock frequency without increasing dissipation. Because the dissipation on the LSI side is lessened, part of the power consumption required for driving the load capacitance is consumed by the series resistance.
Pin Connection Diagram
GND CP 1
1 2
8 7 6 5
VGG (Out) OX 1 OX 2 OX 3
VDD 3 CP 2 4
8
5
.256 (6.52) Max
1
4
.393 (10.0) Max
.300 (7.62)
.150 (3.81)
.100 (2.54)
.070 (1.77) Min
.300 (7.62)

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